Content addressable memory (CAM) devices are often used in network switching and routing systems to determine forwarding destinations and permissions for data packets. A CAM device can be instructed to compare search data obtained from an incoming packet with contents of a forwarding or classification database stored in an associative storage array within the CAM device. If the search data matches an entry in the database, the CAM device generates a match address that corresponds to the location of the matching entry, and asserts a match flag to signal the match. The match address is then typically used to address another storage array, either within or separate from the CAM device, to retrieve a forwarding address or other routing information for the packet.
The associative storage array of a CAM device, a CAM array, is typically populated with CAM cells arranged in rows and columns. Precharged match lines are coupled to respective rows of the CAM cells, and bit line pairs and compare line pairs are coupled to respective columns of the CAM cells. Together, the bit line pairs form a data port for read and write access to address-selected rows of CAM cells, and the compare line pairs form a compare port for inputting search data to the CAM array during search operations. The CAM cells themselves are specialized store-and-compare circuits each including a data storage element to store a constituent data bit of a database entry and a compare circuit for comparing the data bit with a search bit presented on the compare lines. In a typical arrangement, the compare circuits within the CAM cells of a given row are coupled in parallel to the match line for the row, with each compare circuit switchably forming a discharge path to discharge the match line if the data bit and search bit do not match. By this arrangement if any one bit of a database entry does not match the corresponding bit of the search data, the match line for the row is discharged to signal the mismatch. If all the bits of the database entry match the corresponding bits of the search data, the match line remains in its precharged state to signal a match. Because search data is presented to all the rows of CAM cells in each compare operation, a rapid, parallel search for a matching database entry is performed.
In a prior-art ternary CAM array, depicted in FIG. 1, each CAM cell 103 typically includes a mask storage element (MS) to permit storage of a mask state (also called a “don't care” state) in addition to the binary ‘1’ and ‘0’ states stored in the data storage element (DS). The masked state is effected by loading the mask storage element with a mask bit that prevents the compare circuit (CP) from signaling a mismatch between the stored data bit and a search bit (i.e., complementary signals C and /C). Because both mask and data storage elements are provided in each CAM cell, the ternary CAM array provides the flexibility to apply an individually tailored mask pattern to each entry in the database. That is, mask words and data words are stored one-for-one within the ternary CAM array 101 as shown in FIG. 1. In some applications, however, it may be necessary to apply the same mask word to multiple data words. In the CAM application shown in FIG. 2, for example, a set of Z mask words (Mask 1, Mask 2, . . . , Mask Z) are applied, respectively, to Z different mask address ranges (Address Range 1 through Address range Z), with each address range corresponding to multiple rows of CAM cells. Unfortunately, achieving such an arrangement in the ternary CAM array 101 requires that each mask word be stored repeatedly in a sequence of mask write operations directed to each of the addresses within the corresponding mask address range. Repeated storage of the same mask word at different addresses undesirably consumes system resources as a host device must usually initiate a write operation directed to each different address within each different mask range (i.e., providing an instruction, address and mask value for each write operation) and in some cases may also read back each mask word to confirm proper storage.
FIG. 3 illustrates a portion of another prior-art CAM array 160 referred to herein as a shared-mask CAM array. As shown, instead of providing a distinct set of mask storage elements within each row of CAM cells, a row of mask storage elements 163 is shared among multiple rows of CAM cells 161. By this arrangement, a single mask write operation directed to a single row of mask storage elements 163 may be used to store a mask word that is applied across multiple rows of CAM cells (i.e., a range of addresses), thus reducing the number of mask write instructions that need to be issued to apply the same mask word across a given range of addresses. Unfortunately, the shared-mask CAM array 160 is often unsuitable in applications that require different or potentially different mask words to be stored for each data word.